Fin type transistors have been investigated for future generation of devices, such as for sub-22 nm technology. This may be due to, for example, the fact that fin type transistors are conducive to high integration density. However, conventional processes for forming fin type transistors result in large variations in height. This undesirably results in variations in device characteristics across the wafer, reducing reliability and yields. It is desirable to produce fin type devices with reduced height variations as well as enhanced performance.